Timing Optimization of Logic Network Using Gate Duplication
نویسندگان
چکیده
We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication and delay reduction, and then introduce the notion of duplication gain for selecting the good candidate gates to be duplicated. The objective is to obtain the maximum delay reduction with the minimum duplications. The performance of the algorithm is demonstrated with experiments on benchmark circuits. Our approach can also be combined with other technology-independent timing optimizers (such as speed-up) to achieve further delay improvement.
منابع مشابه
A Path Based Algorithm for Timing Driven Logic Replication in FPGA
SUMMARY In this thesis we study the possibility of using logic replication in order to improve timing performance in VLSI design. In particular, we restrict our analysis to FPGA architectures. We describe an algorithm for post-placement timing optimization that exploits the additional freedom degree of logic duplication.
متن کاملTiming Driven Gate Duplication for Delay Optimization
In the past few years gate duplication has been studied as a strategy for cutset minimization in partitioning problems .This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary in-puts(PI) in topologically sorted order evaluating tuples at the input pins...
متن کاملNew full adders using multi-layer perceptron network
How to reconfigure a logic gate for a variety of functions is an interesting topic. In this paper, a different method of designing logic gates are proposed. Initially, due to the training ability of the multilayer perceptron neural network, it was used to create a new type of logic and full adder gates. In this method, the perceptron network was trained and then tested. This network was 100% ac...
متن کاملStatistical Timing Driven Partitioning for VLSI Circuits
In this paper we present statistical-timing driven partitioning for performance optimization. We show that by using the concept of node criticality we can enhance the Fiduccia-Mattheyses (FM) partitioning algorithm to achieve more than 20% improvements in terms of timing, among partitions with the same cut size. By incorporating mechanisms for timing optimization at the partitioning level, we f...
متن کاملEfficient minimization Techniques for Threshold Logic Gate
optimization techniques are discussed using digital logic network using threshold logic. Almost same energy consumption changing speedup is possible using threshold network and many complex functions can be implemented using threshold logic with lesser number of logic gate and logic level for which these optimization techniques becomes popular for digital system design and applications. In this...
متن کامل